A bit huge title for the code question that can be possible

1`timescale 1ns/1ps
2 
3module tb_mux2;
4 
5    logic a;
6    logic b;
7    logic sel;
8    logic y;
9 
10    // Instantiate DUT
11    mux2 dut (
12        .a(a),
13        .b(b),
14        .sel(sel),
15        .y(y)
16    );
17 
18    initial begin
19        // write tb here
20    end
21 
22endmodule