Demux Question

Problem Description

4-to-1 Multiplexer (MUX) in Verilog1

Provide the Verilog code and a testbench for a 4-to-1 Multiplexer.

Component Requirements:

Inputs:
- Four data inputs: $D_0, D_1, D_2, D_3$ (single bit each)
- One 2-bit select signal: $S$ (where $S[1]$ is the MSB and $S[0]$ is the LSB)
Output:
- One data output: $Y$ (single bit)
Functionality: The output $Y$ should equal the data input $D_i$ where $i$ is the decimal value of the select signal $S$.

Language :

Verilog

1module demux_1_to_2 (
2    input D,    // Data Input
3    input S,    // Select Input
4    output Y0,  // Output 0 (Selected when S=0)
5    output Y1   // Output 1 (Selected when S=1)
6);
7 
8   // enter code here
9 
10endmodule

Code Editor Access

Output

Output goes here...