System verilog question

1`timescale 1ns/1ps
2 
3module mux2 (
4    input  logic a,
5    input  logic b,
6    input  logic sel,
7    output logic y
8);
9 
10    always_comb begin
11        if (sel)
12            y = b;
13        else
14            y = a;
15    end
16 
17endmodule